System Verilog for design :

Sutherland, Stuart

System Verilog for design : a guide to using system verilog for hardware design and modeling / Stuart Sutherland, Simon Davidmann and Peter Flake - 2nd - New York Springer 2006 - 418 p.

Includes bibliographical references and index.

9780387333991 (alk. paper) 0387333991 (alk. paper)

2006928944


Verilog (Computer hardware description language)
Electronic digital computers--Design and construction.
Computer simulation.

TK7885.7 / .S875 2006

621.392 SUT-S
An institution deemed to be a University Estd. Vide Sec.3 of the UGC
Act,1956 under notification # F.12-23/63.U-2 of Jun 18,1964

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