Advanced digital design with the Verilog HDL / (Record no. 39623)
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| 000 -LEADER | |
|---|---|
| fixed length control field | nam a22 7a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 190412b2017 xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9789332584464 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 CIL-M |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Ciletti, Michael D. |
| 245 ## - TITLE STATEMENT | |
| Title | Advanced digital design with the Verilog HDL / |
| Statement of responsibility, etc. | Michael D. Ciletti |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | India |
| Name of publisher, distributor, etc. | Pearson |
| Date of publication, distribution, etc. | 2017 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 964 p. |
| 365 ## - TRADE PRICE | |
| Price type code | INR |
| Price amount | 909.00. |
| 500 ## - GENERAL NOTE | |
| General note | This book builds on the student's background from a first course in logic design and focuses on developing, verifying and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing and other applications.<br/><br/>Contents<br/>1. Provides a brief review of basic principles in combinational and sequential logic<br/>2. Focuses on modern digital design methodology<br/>3. Demonstrates the utility of ASM and ASMD charts for behavioral modeling<br/>4. Clearly distinguishes between synthesizable and non-synthesizable loops 5. Provides several problems with a wide range of difficulty after each chapter<br/>6. Combines a solution manual with an on-line repository of additional worked exercises1 Introduction to Digital Design Methodology <br/>2 Review of Combinational Logic Design <br/>3 Fundamentals of Sequential Logic Design<br/>4 Introduction to Logic Design with Verilog<br/>5 Logic Design with Behavioral Models of Combinational<br/>and Sequential Logic <br/>6 Synthesis of Combinational and Sequential Logic<br/>7 Design and Synthesis of Data path Controllers<br/>8 Programmable Logic and Storage Devices<br/>9 Algorithms and Architectures for Digital Processors<br/>10 Architectures for Arithmetic Processors <br/>11 Postsynthesis Design Tasks |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Verilog (Computer hardware description language) |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic circuits--Computer-aided design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Digital electronics |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic design--Data processing |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) | |
| Withdrawn status | |
| Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection code | Home library | Current library | Shelving location | Date acquired | Cost, normal purchase price | Total Checkouts | Total Renewals | Full call number | Barcode | Checked out | Date last seen | Date last checked out | Price effective from | Koha item type |
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| Dewey Decimal Classification | 621 | BITS Pilani Hyderabad | BITS Pilani Hyderabad | General Stack (For lending) | 12/04/2019 | 909.00 | 18 | 3 | 621.395 CIL-M | 38195 | 12/08/2025 | 10/06/2025 | 10/06/2025 | 12/04/2019 | Books |