| 000 | 00709pam a2200217a 44500 | ||
|---|---|---|---|
| 008 | 150502b2001 xxu||||| |||| 00| 0 eng d | ||
| 020 | _a9788131500965 | ||
| 040 |
_cBITS Pilani Hyderabad _aBITS Pilani Hyderabad |
||
| 041 | _aENG | ||
| 082 | _a621.395 DUE-R | ||
| 100 | _aDueck, Robert K. | ||
| 245 |
_aDigital design with CPLD applications and VHDL / _cDueck, Robert K. |
||
| 260 |
_aSingapore _bThomson/Delmar Learning _c2001 |
||
| 300 | _a846 p. | ||
| 650 | _aVHDL (Computer hardware description language) | ||
| 650 | _aLogic design. ﾠ | ||
| 650 | _aProgrammable array logic. ﾠ | ||
| 650 | _aProgrammable logic devices --Design and construction. ﾠ | ||
| 907 | _a621.395 DUE-R | ||
| 942 | _2ddc | ||
| 999 |
_c4786 _d4786 |
||